1. Field of the Invention
The present invention relates to a memory interface apparatus, and more particularly, to a serial memory interface apparatus for memory expansion and shared memory access.
2. Discussion of Related Art
FIG. 1 is a block diagram of a general-purpose central processing unit (CPU) (10) according to a related art.
The general-purpose CPU (10) according to the related art includes one or more cores (11), individual core-dedicated caches (12) (generally referred to as L1 and L2), a shared cache (13) (generally referred to as L3), memory controllers (14), and an input/output (I/O) controller (15).
Since an area occupied by a memory interface is very large, at most two memory controllers (14) may generally be provided in consideration of a chip area.
Data exchange between the shared cache (13) and main memories (20) is performed in hardware, and an auxiliary memory is present in a form of a peripheral (30) under the I/O controller (15).
Here, using a virtual memory technique, physical memory areas may be present in both of main memories and an auxiliary memory, and when viewed from a software perspective, the virtual memory areas may be linearly and continuously present.
Further, an operating system is in charge of data exchange between the physical memory areas of the main memories and the auxiliary memory, and thus a software developer may program software as if the main memories were continuously present.
Meanwhile, a network device (e.g., Gigabit Ethernet, InfiniBand, and the like) is present in the form of the peripheral (30) under the I/O controller (15), and thus data exchange with another CPU may be performed through the network device.
Further, when a main memory dedicated to each CPU is used in another CPU, the CPU that dedicates the main memory and another CPU share and use the main memory by transceiving data using an operating system in a message passing method.
In this case, since a distributed shared memory technique is used by being implemented in software in order to maintain data consistency, the complexity of software is increased. Further, since an I/O is used for memory sharing, a delay time related to the memory sharing is also very long.
Meanwhile, as most I/O controllers (15) used for recent CPUs are serialized, a communication port/line printer terminal (COM/LPT) which is an existing serial bus is replaced by Universal Serial Bus (USB), a peripheral component interconnect (PCI) is replaced by a PCI Express, and a parallel advanced technology attachment (PATA) is replaced by a serial ATA (SATA). Further, an existing parallel signal such as a video graphics array (VGA), a digital visual interface (DVI), and the like, which is a signal used to transmit a display in a graphic processor, is also replaced by a serial interface such as a high-definition multimedia interface (HDMI), a display port, and the like.
However, specifically, since a memory interface part that is the greatest area occupied in the CPU requires a high bandwidth, serialization has not progressed and a method in which 100 to 200 parallel signal lines are used is used without change.
Therefore, a memory signal line acts as a critical factor when a flexible computer system is configured. Specifically, when several CPUs access a common memory area, a current system has to rely on an I/O interface having a slow speed, many access steps, and a complex processing rather than using a memory interface having a faster access speed.
In this regard, Korean Patent Application Publication No. 10-2005-0078691 (Title of the Invention: MEMORY CONTROLLER AND MEMORY MODULE USING A SERIAL INTERFACE) discloses a technique in which a serial interface method is used for a data transceiving operation between a memory controller and a memory module which are included in a personal computer and the like.